.org 0x00
rjmp init

.org 0x01
rjmp increment


init:
cbi DDRB,0
sbi DDRB,2

ldi r17,0b00000010
out MCUCR,r17

ldi r17,0b01000000
out GIMSK,r17

sei

ldi r24,0

loop:

sbi PORTB,2
rcall delay

cbi PORTB,2
rcall delay

rjmp loop




delay:
rjmp vibor 
vv:			              
out TCNT0, r18				
out TCCR0B, r20			   
a:
in r19, TIFR0				
sbrs r19, 1		            	
rjmp a				        
ldi r21, 0b00000000			
out TCCR0B, r21
ldi r22, 0b00000010			
out TIFR0, r22
ret        

vibor:
cpi r24,0
breq n1
cpi r24,1
breq n2
cpi r24,2
breq n3
cpi r24,3
breq n4
cpi r24,4
breq n5
cpi r24,5
breq n6
cpi r24,6
breq n7
cpi r24,7
breq n8
cpi r24,8
breq n9
cpi r24,9
breq n10
ret

n1:
ldi r18, 0			        
ldi r20, 0b00000101
rjmp vv
n2:
ldi r18, 50			        
ldi r20, 0b00000101
rjmp vv
n3:
ldi r18, 100			        
ldi r20, 0b00000101
rjmp vv
n4:
ldi r18, 150			        
ldi r20, 0b00000101
rjmp vv
n5:
ldi r18, 200			        
ldi r20, 0b00000101
rjmp vv
n6:
ldi r18, 250			        
ldi r20, 0b00000101
rjmp vv
n7:
ldi r18, 0			        
ldi r20, 0b00000010
rjmp vv
n8:
ldi r18, 50			        
ldi r20, 0b00000010
rjmp vv
n9:
ldi r18, 100			        
ldi r20, 0b00000010
rjmp vv
n10:
ldi r18, 150			        
ldi r20, 0b00000010
rjmp vv


increment:
inc r24
cpi r24,10
breq sbros
reti

sbros:
ldi r24,0
reti