Вообще с платой шел вот такой вот код
Но что-то не получается у меня в нем разобраться
Были бы читаемые комментарии
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity top is
port
(
clkin:in std_logic;--clkin=40M
resetin: in std_logic;
rxd:in std_logic;--дёІиЎЊиѕ“е…Ґж•°жЌ®
--led:out std_logic_vector(2 downto 0);--led控制
txd:out std_logic--дёІиЎЊиѕ“е‡єж•°жЌ®
);
end top;
architecture behave of top is
component gen_div is--分频元件调用声жЋ
generic(div_param:integer:=156);--312分频的,产生16*9600的时钟
port
(
clk:in std_logic;
bclk:out std_logic;
resetb:in std_logic
);
end component;
component uart_t is--串口发送元件调用声жЋ
port
(
bclkt,resett,xmit_cmd_p:in std_logic;
txdbuf:in std_logic_vector(7 downto 0);
txd:out std_logic;
txd_done:out std_logic
);
end component;
component uart_r is--串口接收元件调用声жЋ
port
(
bclkr,resetr,rxdr:in std_logic;
r_ready:out std_logic;
rbuf:out std_logic_vector(7 downto 0)
);
end component;
component narr_sig is--信号窄化元件调用声жЋ
port
(
sig_in:in std_logic;
clk:in std_logic;
resetb:in std_logic;
narr_prd:in std_logic_vector(7 downto 0);--narrдїЎеЏ·жЊЃз»зљ„е‘Ёжњџж•°(以clkдёєе‘Ёжњџ)
narr_sig_out:out std_logic
);
end component;
----------------------------------------------------------
signal clk_b:std_logic;--16倍的波特率时钟
--еЏ‘йЂЃз›ёе…іеЇ„ее™Ё--
signal xmit_p:std_logic;--ж–°дёЂиЅ®еЏ‘йЂЃеђЇеЉЁдїЎеЏ·
signal xbuf: std_logic_vector(7 downto 0);--еѕ…еЏ‘йЂЃж•°жЌ®зј“е†ІеЊє
signal txd_done_iner:std_logic;--дёЂеё§ж•°жЌ®еЏ‘йЂЃе®ЊжЇ•ж ‡еї—
--接收相关寄ее™Ё--
signal rev_buf: std_logic_vector(7 downto 0);--接收数据缓冲区
signal rev_ready:std_logic;--дёЂеё§ж•°жЌ®жЋҐж”¶е®ЊжЇ•ж ‡еї—
--led 控制--
signal led_tmp:std_logic_vector(2 downto 0);
------------------------------------------------------------
begin
uart_baud:
gen_div port map--分频模块例化
(
clk=>clkin,
resetb=>not resetin,
bclk=>clk_b
);
----------
uart_transfer:
uart_t port map--дёІеЏЈеЏ‘йЂЃжЁЎеќ—дѕ‹еЊ–
(
bclkt=>clk_b,
resett=>not resetin,
xmit_cmd_p=>xmit_p,
txdbuf=>xbuf,
txd=>txd,
txd_done=>txd_done_iner
);
uart_receive: --串口接收元件例化
uart_r port map
(
bclkr=>clk_b,
resetr=>not resetin,
rxdr=>rxd,
r_ready=>rev_ready,
rbuf=>rev_buf
);
narr_rev_ready: --зЄ„еЊ–rev_readyдїЎеЏ·еђЋз»™xmit_p
narr_sig
port map
(
sig_in=>rev_ready,--иѕ“е…ҐйњЂзЄ„еЊ–дїЎеЏ·
clk=>clk_b,
resetb=>not resetin,
narr_prd=>X"03",--narrдїЎеЏ·й«з”µе№іжЊЃз»зљ„е‘Ёжњџж•°(以clkдёєе‘Ёжњџ)
narr_sig_out=>xmit_p--иѕ“е‡єзЄ„еЊ–еђЋдїЎеЏ·
);
--------------------------
--led<=led_tmp;
--------------------------
r_t_data: --把接收到的数据发送出去
process(rev_ready,resetin,rev_buf,led_tmp,clk_
begin
if resetin='0' then--е¤ЌдЅЌж—¶е…ЁзЃ
--led_tmp<="000";
else
if rising_edge(rev_ready) then
xbuf<=rev_buf;--иЈ…иЅЅж•°жЌ®
--led_tmp<=not led_tmp;
end if;
end if;
end process;
----------------------------------------------------------
end behave;
