Фильтр На Vhdl

[Green_line]

У меня задача: реализовать фильтр на VHDL: необходимо произвести линейную фильтрацию. Для фильтрации берется стандартная картинка в RGB цвете 24 битная, которая затем преобразуется с помощью сторонних программных средств в 32 битную картинку с 3-мя оттенками серого, которая и подается на вход фильтра(чтение из файла), фильтр сделав необходимую фильтрацию отдает ее на выход(запись в файл). Заданная задача у меня реализован0, а но запись в файл производиться неправильно - полученная картинка не соответствует той, которая была на входе. Возможно, проблема с коэффициентом нормализации фильтра. Я не знаю, как его написать. Буду рад услышать совет.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Filter is
Port (
Clock		: in	std_logic;
Reset		: in	std_logic;

data		: in	std_logic_vector(7 downto 0);
input_En	: in	std_logic;

filteredData: out	std_logic_vector(7 downto 0);
out_En		: out	std_logic
 );
end Filter;


architecture Filter of Filter is

component Multipl is
Port (
Clock	: in std_logic;

A		: in std_logic_vector(7 downto 0);
B		: in std_logic_vector(7 downto 0);
Result	: out std_logic_vector(15 downto 0);

Set		: in std_logic;
Res_Rdy	: out std_logic
 );
end component;														

signal K0	:	std_logic_vector(7 downto 0):= "00000000";			
signal K1	:	std_logic_vector(7 downto 0):= "00000000";			
signal K2	:	std_logic_vector(7 downto 0):= "00000000";			
signal K3	:	std_logic_vector(7 downto 0):= "00001001";			
signal K4	:	std_logic_vector(7 downto 0):= "00000000";			
signal K5	:	std_logic_vector(7 downto 0):= "00000000";			
signal K6	:	std_logic_vector(7 downto 0):= "00000000";			

signal Norm	:	std_logic_vector(7 downto 0):= "00000010";			

signal data0	:	std_logic_vector(7 downto 0):= "00000000";
signal data1	:	std_logic_vector(7 downto 0):= "00000000";
signal data2	:	std_logic_vector(7 downto 0):= "00000000";
signal data3	:	std_logic_vector(7 downto 0):= "00000000";
signal data4	:	std_logic_vector(7 downto 0):= "00000000";
signal data5	:	std_logic_vector(7 downto 0):= "00000000";
signal data6	:	std_logic_vector(7 downto 0):= "00000000";

signal mult0	:	std_logic_vector(15 downto 0):= "0000000000000000";
signal mult1	:	std_logic_vector(15 downto 0):= "0000000000000000";
signal mult2	:	std_logic_vector(15 downto 0):= "0000000000000000";
signal mult3	:	std_logic_vector(15 downto 0):= "0000000000000000";
signal mult4	:	std_logic_vector(15 downto 0):= "0000000000000000";
signal mult5	:	std_logic_vector(15 downto 0):= "0000000000000000";
signal mult6	:	std_logic_vector(15 downto 0):= "0000000000000000";

signal sum0		:	std_logic_vector(16 downto 0):= "00000000000000000";
signal sum1		:	std_logic_vector(17 downto 0):= "000000000000000000";
signal sum2		:	std_logic_vector(18 downto 0):= "0000000000000000000";
signal sum3		:	std_logic_vector(19 downto 0):= "00000000000000000000";
signal sum4		:	std_logic_vector(20 downto 0):= "000000000000000000000";
signal sum5		:	std_logic_vector(21 downto 0):= "0000000000000000000000";	
signal count	:	std_logic_vector(3 downto 0) := "0000";
signal reg		: 	std_logic_vector(12 downto 0) := "0000000000000";
signal Res_Rdy	:	std_logic;
begin	

filt0 :	Multipl
Port map(
Clock 	=> Clock,
A		=> K0,
B		=> data0,
Result	=> mult0,
Res_Rdy	=> Res_Rdy,
Set		=> '1'
);

filt1 :	Multipl
Port map(
Clock 	=> Clock,
A		=> K1,
B		=> data1,
Result	=> mult1,
Res_Rdy	=> Res_Rdy,
Set		=> '1'
);

filt2 :	Multipl
Port map(
Clock 	=> Clock,
A		=> K2,
B		=> data2,
Result	=> mult2,
Res_Rdy	=> Res_Rdy,
Set		=> '1'
);

filt3 :	Multipl
Port map(
Clock 	=> Clock,
A		=> K3,
B		=> data3,
Result	=> mult3,
Res_Rdy	=> Res_Rdy,
Set		=> '1');

filt4 :	Multipl
Port map(
Clock 	=> Clock,
A		=> K4,
B		=> data4,
Result	=> mult4,
Res_Rdy	=> Res_Rdy,
Set		=> '1'
);

filt5 :	Multipl
Port map(
Clock 	=> Clock,
A		=> K5,
B		=> data5,
Result	=> mult5,
Res_Rdy	=> Res_Rdy,
Set		=> '1'
);

filt6 :	Multipl
Port map(
Clock 	=> Clock,
A		=> K6,
B		=> data6,
Result	=> mult6,
Res_Rdy	=> Res_Rdy,
Set		=> '1'
);

process(Clock)
begin		
	if (rising_edge(Clock)) then
		filteredData 	<= sum5(11 downto 4);
		sum0		<= '0'&mult0 + mult1;			
		sum1		<= '0'&sum0 + mult2;
		sum2		<= '0'&sum1 + mult3;	
		sum3		<= '0'&sum2 + mult4;
		sum4		<= '0'&sum3 + mult5; 	
		sum5		<= '0'&sum4 + mult6;	

	end if;				
end process;

--1		
process(Clock, Reset)
begin
	if(Reset = '1') then
		Res_Rdy	<= '0';	

elsif(rising_edge(Clock)) then
	if (input_En ='1') then
		data0 <= data;
	end if;
	 reg(0)<= input_En;
end if;
end process;
--2	
process(Clock)
begin
	if (rising_edge(Clock)) then
		reg(1)<= reg(0);
		data1 <= data0;
	end if;
end process;	

--3	
process(Clock)
begin		
	if (rising_edge(Clock)) then
		reg(2)<= reg(1);
		data2 <= data1;	
	end if;				
end process;

--4	
process(Clock)
begin		
	if (rising_edge(Clock)) then
		reg(3)<= reg(2);
		data3 <= data2;	
	end if;				
end process;	

--5	
process(Clock)
begin		
	if (rising_edge(Clock)) then
		reg(4)<= reg(3);
		data4 <= data3;	
	end if;				
end process;

--6	
process(Clock)
begin		
	if (rising_edge(Clock)) then
		reg(5)<= reg(4);
		data5 <= data4;	
	end if;				
end process;	

--7	
process(Clock)
begin		
	if (rising_edge(Clock)) then
		reg(6)<= reg(5);
		data6 <= data5;	
	end if;				
end process;	
--8
process(Clock)
begin		
	if (rising_edge(Clock)) then
		reg(7)<= reg(6);
	end if;				
end process;
--9
process(Clock)
begin		
	if (rising_edge(Clock)) then
		reg(8)<= reg(7);

	end if;				
end process;
--10
process(Clock)
begin		
	if (rising_edge(Clock)) then
		reg(9)<= reg(8);
	end if;				
end process;

--11
process(Clock)
begin		
	if (rising_edge(Clock)) then
		reg(10)<= reg(9);
	end if;				
end process; 	
--11
process(Clock)
begin		
	if (rising_edge(Clock)) then
		reg(11)<= reg(10);
	end if;				
end process;
--11
process(Clock)
begin		
	if (rising_edge(Clock)) then
		reg(12)<= reg(11);
		out_En <= reg(12);
	end if;				
end process;
end Filter;

[Реклама]

Реклама: ООО ТД Промэлектроника, ИНН: 6659197470, Тел: 8 (800) 1000-321