[Vhdl Mux 4 В 1, 8 Bit]

library ieee;
use ieee.std_logic_1164.all;
entity mux_cxem_net is
port(A,B,C,D:in std_logic_vector(7 downto 0);
 ADR:in std_logic_vector(1 downto 0);
Y:out std_logic_vector(7 downto 0));
end entity mux_cxem_net;
architecture body_1 of mux_cxem_net is
begin
Y<=A when ADR="00" else
 B when ADR="01" else
C when ADR="10" else
D when ADR="11" else
(others=>'X');
end architecture body_1;
architecture body_2 of mux_cxem_net is
begin
with ADR select
Y<=A when "00",
 B when "01",
C when "10",
D when others;
end architecture body_2;
architecture body_3 of mux_cxem_net is
begin
process(ADR,A,B,C,D)
begin
if ADR="00" then
 Y<=A;
elsif ADR="01" then
Y<=B;
elsif ADR="10" then
Y<=C;
else
Y<=D;
 end if;
end process;
end architecture body_3;
architecture body_4 of mux_cxem_net is
begin
process(ADR,A,B,C,D)
begin
case ADR is
 when "00" => Y <= A;
when "01" => Y <= B;
when "10" => Y <= C;
when others => Y <=D;
end case;
end process;
end architecture body_4;

все четыре архитектурных тела описывают одно и то же-- 8битный мультиплексор 4-1. используйте любое.